Exemplary embodiments of the present invention relate to a data output circuit of a semiconductor memory device, and more particularly, to a data output circuit for correcting a duty ratio of an output clock, and a data output method thereof.
Synchronous semiconductor memory devices are designed to operate in synchronization with an external clock. Double data rate (DDR) synchronous memory devices successively process two-bit data in one clock cycle in synchronization with the rising and falling edges of an external clock. The DDR synchronous memory devices may use a delay locked loop (DLL) to implement accurate data input/output timings.
In such synchronous semiconductor memory devices, data are inputted and outputted based on a clock and it is desirable to exactly control a duty ratio of a clock. If a duty ratio of a clock is not accurately controlled, data margin may not be ensured, causing distortion of data.
A duty ratio refers to a ratio of a high level duration to a low level duration in one clock cycle. For example, the duty ratio of (50:50) means that a high level duration is equal to a low level duration in one clock cycle.
FIG. 1 is a configuration diagram of a conventional data output circuit.
Referring to FIG. 1, the conventional data output circuit includes a DLL 110, a repeater 130, an output control unit 170, and an output unit 190.
The DLL 110 compares a phase of an external clock CLK with a phase of an internal clock, synchronizes the phase of the internal clock with the phase of the external clock CLK, corrects a duty ratio of the internal clock to, for example, 50:50, and outputs first internal clocks RCLK_DLL1 and FCLK_DLL1.
The repeater 130 removes distortion of the first internal clocks RCLK_DLL1 and FCLK_DLL1 outputted from the DLL 110, and outputs output clocks RCLK_DO and FCLK_DO.
The output unit 190 includes a data output section 193 and a data strobe signal output section 191, and outputs data DQ and data strobe signals DQS and DQSB in response to the output clocks RCLK_DO and FCLK_DO. The data strobe signal output section 191 generates the data strobe signals DQS and DQSB by using the output clocks RCLK_DO and FCLK_DO, and outputs the generated signals to, for example, a memory controller (not shown). The data output section 193 outputs the data DQ to the memory controller (not shown) in response to the output clocks RCLK_DO and FCLK_DO and the data strobe signals DQS and DQSB.
Since the data output section 193 and the data strobe signal output section 191 output the data DQ and the data strobe signals DQS and DQSB in response to the output clocks RCLK_DO and FCLK_DO, respectively, the phase of the data DQ and the phase of the data strobe signals DQS and DQSB are synchronized with each other. The memory controller receives the data DQ outputted from the data output section 193, based on the data strobe signals DQS and DQSB outputted from the data strobe signal output section 191.
The output control unit 170 controls the output unit 190 and the repeater 130 using a clock enable signal CKEN representing an operation of the semiconductor memory device, such as a read operation.
FIG. 2 is a configuration diagram of the DLL 110 illustrated in FIG. 1.
Referring to FIG. 2 the DLL 110 includes a phase comparison unit 201, a delay control unit 203, a replica model unit 205, and a duty ratio correction unit 207.
The phase comparison unit 201 compares a phase of an external clock CLK with a phase of a feedback clock FB_CLK outputted from the replica model unit 205, which models a clock delay in the inside of the semiconductor memory device, and outputs a comparison signal CMP to the delay control unit 203. The comparison signal CMP represents a phase difference between the external clock CLK and the feedback clock FB_CLK.
The delay control unit 203 delays the external clock CLK by a first delay amount DD_1 (shown in FIG. 3) in response to the comparison signal CMP in order to synchronize the phase of the external clock CLK with the phase of the feedback clock FB_CLK, and outputs a delayed clock CLK_DD. The duty ratio correction unit 207 corrects a duty ratio of the delayed clock CLK_DD, and outputs a corrected clock, a first rising internal clock RCLK_DLL1, to the replica model unit 205.
Through the above-described procedures, the delay of the delay control unit 203 and the delay of the replica model unit 205 are mirrored or manifested in the feedback clock FB_CLK outputted from the replica model unit 205, so that the phase of the feedback clock FB_CLK is synchronized with the phase of the external clock CLK. At this time, the delayed clock CLK_DD in which the delay of the delay control unit 203 is mirrored is delay-locked.
The duty ratio correction unit 207 includes a correction section 209 and a detection section 211.
The detection section 211 detects duty ratios of the first internal clocks RCLK_DLL1 and FCLK_DLL1 outputted from the correction section 209, and generates detection signals DCC and DCCB representing the duty ratios of the first internal clocks RCLK_DLL1 and FCLK_DLL1.
The correction section 209 corrects the duty ratio of the delayed clock CLK_DD, which is outputted from the delay control unit 203, in response to the detection signals DCC and DCCB, and outputs first internal clocks RCLK_DLL1 and FCLK_DLL1 whose phases are opposite to each other and whose duty ratios are corrected to, for example, 50:50.
However, when the distortion of the duty ratios of the first internal clocks RCLK_DLL1 and FCLK_DLL1 is out of the allowable duty ratio correction range of the duty ratio correction unit 207, the conventional DLL 110 outputs the first internal clocks RCLK_DLL and FCLK_DLL whose duty ratios are not accurately corrected to 50:50. Since the conventional data output circuit uses the first internal clocks RCLK_DLL1 and FCLK_DLL1, whose duty ratios are not accurately corrected, as the output clocks RCLK_DO and FCLK_DO for data output, the data output unit 190 outputs data based on the data strobe signals DQS and DQSB whose duty ratios are distorted. Consequently data margin may be reduced and thus output data of the semiconductor memory device may be distorted.
Furthermore, even though the correction section 209 of the DLL 110 accurately corrects the duty ratios of the first internal clocks RCLK_DLL1 and FCLK_DLL1, the duty ratios of the first internal clocks RCLK_DLL1 and FCLK_DLL1 may be distorted by external noises, distortion of transmission lines, or PVT variations, while passing through various internal circuits. Consequently, data margin may be reduced and thus output data of the semiconductor memory device may be distorted.
FIG. 3 is a timing diagram explaining a data output operation of the data output circuit shown in FIG. 1.
The DLL 110 delays the external clock CLK by the first delay amount DD_1 and generates the first internal clocks RCLK_DLL1 and FCLK_DLL1. For example, although the duty ratio of the external clock CLK is not 50:50, the duty ratios of the first internal clocks RCLK_DLL1 and FCLK_DLL1 are corrected to 50:50 by the duty ratio correction unit 207.
However, while the first internal clocks RCLK_DLL1 and FCLK_DLL1 pass through several internal circuits including the repeater 130, their duty ratios may be distorted by external noises, distortion of transmission lines, or PVT variations. Upon receipt of the distorted internal clocks RCLK_DLL1 and FCLK_DLL1 the data output circuit uses the first internal clocks RCLK_DLL1 and FCLK_DLL1, whose duty ratios are distorted, as the output clocks RCLK_DO and FCLK_DO. The output unit 190 outputs data DQ in synchronization with the rising edges of the output clocks RCLK_DO and FCLK_DO whose duty ratios are distorted. Consequently, data margin is reduced and jitter characteristic is degraded, resulting in distortion of the output data DQ.
Since the conventional data output circuit outputs data based on the data strobe signals whose duty ratios are distorted, data margin may be reduced and output data of the semiconductor memory device may be distorted.